1. Field of the Invention
The present invention relates to a data processing apparatus for effecting a pipeline processing operation of data according to instructions of a memory, and more particularly, to a data processing apparatus for processing instructions for extending the data shorter than the register length.
2. Description of the Prior Art
The data processing apparatuses as well as the microcomputers come into general use due to the development of the recent electronic art, so as to be used in all the fields.
The conventional data processing apparatuses can be chiefly divided into a CISC (Complex Instruction Set Computer) type characterized by multiple types of instructions and a RISC (Reduced Instruction Set Computer) type characterized by higher speed through limitation of the instruction types. For example, TRON, MC 68040, and so on are the former, while SPARC, MIPS and so on are the latter. They are respectively of pipeline construction designed to shorten the apparent execution time. The pipeline divides the processing of the instructions into at least reading, decoding, execution stages to execute them in parallel.
FIG. 7 shows a block diagram of a microcomputer as the conventional data processing apparatus. The data processing apparatus is composed of five stage pipeline construction comprising five stages, an instruction fetch stage (hereinafter referred to as IF stage), a decode and register reading stage (hereinafter, as DEC stage), an operation and operand address calculation stage (hereinafter, as EX stage), a memory access stage (hereinafter, as MEM stage), and a register write back stage (hereinafter, as WB stage).
Referring now to FIG. 7, reference numeral 5 is a ROM for accommodating a machine language program, reference numeral 6 is an I latch for accommodating an machine language instruction (hereinafter, as instruction) taken out from the ROM 5, reference numeral 7 is an instruction decoder for deciding an instruction retained in the I latch 6 to control each portion of the microcomputer 4, reference numeral 8 is a register file for accommodating the operand or the address for specifying the operand, reference numeral 26 is a D selector for selecting one from 2 inputs of one portion of the content of the I latch 6 and the output of the register file 8, reference numeral 13 is a D1 latch for accommodating the output of the D selector 26, reference numeral 14 is a D2 latch for accommodating the output of the register file 8, reference numeral 15 is an arithmetic logic unit for effecting arithmetic logical operation with the use of the contents of the D1 latch 13 and the D2 latch 14, reference numeral 18 is an E latch for accommodating the output of the arithmetic logic unit 15, reference numeral 19 is a RAM from which the data is read with the value of the E latch 18 as the address input, reference numeral 20 is a M selector for selecting one from the two inputs of the value of the E latch 18 and the output of the RAM 19, reference numeral 27 is an extension unit for zero-extending or sign-extending the lower 8 bits or the lower 16 bits of the output of the M selector 20 into 32 bits, reference numeral 21 is a M latch for accommodating the output of the extension unit 27. The input/output of all the components except for the ROM 5, the I latch 6, the instruction encoder 7 has a 32-bit width.
The conventional data processing apparatus of such construction as described above loads the 8-bit or 16-bit data for zero-extending or sign-extending it into 32 bits, and assigns a single machine language instruction respectively to the commands of the assembly language program to accommodate in the register. The instruction is encoded by the instruction decoder 7 and is executed as follows in the MEM stage. Namely, the 8-bit or 16-bit data specified by the instruction is read from the RAM 19 and further, is zero-extended or sign-extended into the 32-bit length by the extension unit 27 and the results are accommodated in the register file 8.
In the data processing apparatus having the pipe line construction, it is demanded that the processing time of each stage of the pipeline should be approximately equal and shorted as much as possible. But in the above described conventional data processing apparatus, the processing time of the MEM stage becomes longer than those of the other stages, because it is composed of the access time of the RAM 19, the delay time of the M selector 20, the delay time of the extension unit 27, the set up time of the M latch 21, and the wiring propagation delay time among them. As a result, the upper bound of the operation clock frequency has a problem in that it is controlled lower by the processing time of the MEM sage, thereby being difficult to improve the performance. Also, to make the processing time in the MEM stage approximately equal to the processing time of the other stage, the engagement of the high speed RAM 19 extremely shorter in the access time is demanded, with a problem in that the cost and the consumption power are increased.